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HT49C10 8-Bit Microcontroller
Features
* * * * * * * * * * *
Operating voltage: 2.2V~5.2V Eight bidirectional I/O lines Six input lines Two external interrupt input 8-bit programmable timer/event counter withPFD(programmablefrequencydivider) Watchdog timer On-chip crystal and RC oscillator 1K14 program memory ROM 648 data memory RAM Real Time Clock (RTC) 8-bit prescaler for RTC
* * * * * * * * * *
Buzzer output Halt function and wake-up feature reduce power consumption LCD driver with 193 or 184 segments 4-level subroutine nesting Bit manipulation instruction 14-bit table read instruction Up to 1ms instruction cycle with 4MHz system clock 63 powerful instructions All instructions in 1 or 2 machine cycles 48-pin SSOP package
General Description
The HT49C10 is an 8-bit high performance single chip microcontroller. Its single-cycle instruction and two-stage pipeline architecture make it suitable for high speed applications. The device is also suited for multiple LCD low power applications among which are calculators, clock timers, games, scales, leisure products, other hand held LCD products, and battery systems in particular.
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Block Diagram
In te rru p t C ir c u it P ro g ra m ROM P ro g ra m C o u n te r STACK IN T C TM RC TM R T im e r C L K M U X
TM R
In s tr u c tio n R e g is te r
MP
M U
RTC X DATA M e m o ry W DT T im e B a s e M U X
S Y S C L K /4 OSC3 OSC4
RTC OSC
W DT OSC PORT B
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R PB3~PB5
STATUS
PB
S h ifte r PORT A BP
OSC2
OS RE VD VS S
S D
C1
ACC LCD M e m o ry L C D D R IV E R
PA
PA0 PA1 PA2 PA3 PA4
/B Z /B Z /P F D ~PA7
C O M 0~ COM2
C O M 3/ SEG 18
SEG 0~ SEG 17
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Pin Assignment
P A 0 /B Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P A 1 /B Z PA2 P A 3 /P F D PA4 PA5 PA6 PA7 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R PB3 PB4 PB5 VSS VLCD V1 V2 C1 C2 COM0 COM1 COM2 S E G 1 8 /C O M 3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 RES OSC1 OSC2 VDD OSC3 OSC4 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17
H T49C 10 48 SSO P
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Pad Assignment
PA3/PFD PA1/BZ PA0/BZ OSC1 OSC2 RES VDD PA4 1 PA5 PA6 PA7 PB0/INT0 PB1/INT1 PB2/TMR PB3 PB4 PB5 VSS VLCD V1 12 13 14 15 V2 C1 16 17 C2 COM0 18 19 COM1 COM2 20 21 SEG18/COM3 SEG17 22 SEG16 23 24 SEG15 SEG14 25 26 SEG13 SEG12 2 3 4 5 6 7 8 9 10 11 (0,0) 38 37 36 35 34 33 32 31 30 29 28 27 SEG11 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 PA2
48 47 46 45 44
43
42
41
40
OSC3
39
OSC4
* The IC substrate should be connected to VSS in the PCB layout artwork.
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Pad Description
Pad No. Pad Name I/O Mask Option Description PA0~PA7 constitute an 8-bit bidirectional input/ output port with Schmitt trigger input capability. Each bit on port can be configured as wake-up input by mask option. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) and with or without pull-high resistor by mask option, PA4~PA7 always pull-high and NMOS (input/output). Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O pin or a PFD output also by mask option. PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port are pull-high resistor. Of the six bits, PB0 can be set as input pin or external interrupt control pin (INT0) by software application. PB1 can be set as input pin or an external interrupt control pin (INT1) by software application. While PB2 can be set as input pin or timer/event counter input pin also by software application. Negative power supply, GND LCD power supply Voltage pump SEG18 can be set as segment or common output driver for LCD panel by mask option. COM2~COM0 are outputs for LCD panel plate. LCD driver outputs for LCD panel segments Real time clock oscillators Positive power supply
45 46 47 48 1~4
PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7
I/O
Wake-up Pull-high or None CMOS or NMOS
5 6 7 8~10
PB0/INT0 PB1/INT1 PB2/TMR PB3~PB5
I
3/4
11 12 13~16 20 19~17 21~38 39 40 41 42 43 44
VSS VLCD V1,V2,C1,C2 SEG18/COM3 COM2~COM0 SEG17~SEG0 OSC4 OSC3 VDD OSC2 OSC1 RES
I I I O O O I 3/4 O I I
3/4 3/4 3/4 1/3 or 1/4 Duty 3/4 3/4 3/4
OSC1 and OSC2 are connected to an RC network or a Crystal or crystal (by mask option) for the internal system clock. RC In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. 3/4 Schmitt trigger reset input, active low
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Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 IDD2 ISTB1 ISTB2 VIL VIH VIL1 VIH1 IOL IOH RPH Parameter Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Standby Current (RTC Enable, LCD On) Standby Current (RTC Disable, LCD Off) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES, INT0, INT1, TMR) Input High Voltage (RES, INT0, INT1, TMR) I/O Ports Sink Current I/O Ports Source Current Pull-high Resistance of I/O Ports and INT0, INT1 Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load, fSYS=4MHz No load, fSYS=2MHz No load, system Halt No load, system Halt 3/4 3/4 3/4 3/4 RES=0.5VDD INT0/1=0.3VDD TMR=0.3VDD 0.8VDD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V 3/4 3/4 Min. 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.1 3.5 0 0 2.4 4.0 1.5 4 -1 -2 40 10 Typ. 3/4 0.7 2 0.5 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.5 6 -1.5 -3 60 30
Ta=25C Max. 5.2 1.5 3 1 2 5 10 1 2 0.9 1.5 3 5 1.5/0.9 2.5/1.5 3 5 3/4 3/4 3/4 3/4 80 50 Unit V mA mA mA mA mA mA mA mA V V V V V V V V mA mA mA mA kW kW
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A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER Parameter System Clock (Crystal OSC) System Clock (RC OSC) Timer I/P Frequency (TMR) Test Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Power-up or wake-up from halt 3/4 Min. 455 455 400 400 0 0 45 35 1 3/4 1 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 Max. 4000 4000 2000 3000 4000 4000 180 130 3/4 3/4 3/4 Ta=25C Unit kHz kHz kHz kHz kHz kHz ms ms ms tSYS ms
tWDTOSC Watchdog Oscillator tRES tSST tINT External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS
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Functional Description
Execution flow The system clock is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1024 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates program transfer by loading the address corresponding to each instruction.
T1 T2 T3 T4 T1 T2
The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program memory - ROM The program memory (ROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 102414 bits which are addressed by the PC and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
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* Location 008H
000H 004H 008H 00C H 010H 014H
Location 008H is reserved for the external interrupt service program. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t0 s u b r o u tin e E x te r n a l in te r r u p t1 s u b r o u tin e T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e T im e b a s e in te r r u p t R T C in te r r u p t P ro g ra m ROM
Location 00CH is reserved for the timer/event counter interrupt service program. If a timer interrupt resulting from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
Location 010H is reserved for the time base interrupt service program. If a time base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010H.
* Location 014H
3FFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 3
Program memory
* Table location
Location 014H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H. Mode Initial reset External interrupt 0 External interrupt 1 Timer/event Counter overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine *9 #9 S9 *8 #8 S8
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the conProgram Counter
*9 0 0 0 0 0 0
*8 0 0 0 0 0 0
*7 0 0 0 0 0 0 @7 #7 S7
*6 0 0 0 0 0 0 @6 #6 S6
*5 0 0 0 0 0 0 @5 #5 S5
*4 0 0 0 0 1 1 @4 #4 S4
*3 0 0 1 1 0 0 @3 #3 S3
*2 0 1 0 1 0 1 @2 #2 S2
*1 0 0 0 0 0 0 @1 #1 S1
*0 0 0 0 0 0 0 @0 #0 S0
PC+2
Program counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits
9
S9~S0: Stack register bits @7~@0: PCL bits
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tents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (table higher-order byte register) (08H). Only the destination of t h e l ow er - or d er b y te i n t he t a b l e i s well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining two bits are both read as 0. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require two cycles to complete the operation. These areas may function as a normal ROM dependingupontherequirements. Stack register - STACK The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into four levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commencement of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the inInstruction(s) TABRDC [m] TABRDL [m] terrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent four return addresses are stored). Data memory - RAM The data memory (RAM) is designed with 818 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. Of the two types of functional groups, the special function registers consist of an indirect addressing register 0 (00H), a memory pointer register 0 (MP0; 01H), an indirect addressing register 1 (02H), a memory pointer register 1 (MP1;03H), a bank pointer (BP;04H), an accumulator (ACC;05H), a program counter lower-order byte register (PCL;06H), a table pointer (TBLP;07H), a table higher-order byte register (TBLH;08H), a real time clock control register (RTCC;09H), a status register (STATUS;0AH), an interrupt control register 0 (INTC0;0BH), a timer/event counter (TMR;0DH), a timer/event counter control register (TMRC; 0EH), I/O registers (PA;12H, PB;14H), and interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to 5FH, is used for data and control information under instruction commands. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except for some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer Table Location *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *9~*0: Table location bits @7~@0: Table pointer bits
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P9~P8: Current program counter bits
HT49C10
register 0 (MP0;01H) or the memory pointer register 1 (MP1;03H).
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H G e n e ra l P u rp o s e D a ta M e m o ry (6 4 B y te s ) 5FH IN T C 1 :U nused R e a d a s "0 0 " PB PA TM R TM RC S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0
MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H, while, writing it leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect addressing registers. The bit 7 of MP0 and MP1 are undefined and reading will return the result 1 . Any writing operation to MP0 and MP1 will only transfer the lower 7-bit data. Only MP0 can be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to ALU operations. It is also mapped to location 05H of the RAM and is capable of carrying out immediate data operations. The data movement between two data memory locations has to pass through the ACC. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations
(ADD, ADC, SUB, SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS The status register (0AH) is 8-bit wide and contains a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PD flags, bits in the status register can be altered by instructions, similar to other registers. Data written into the status reg11 September 28, 1999
RAM mapping Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and
HT49C10
Labels C Bits 0 Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Undefined, read as 0 STATUS register ister does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, precautions should be taken to save it properly. Interrupts The HT49C10 provides two external interrupts, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other
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AC Z OV PD TO 3/4
1 2 3 4 5 6, 7
interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC0 or of INTC1 in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts have the wake-up capability. When an interrupt is serviced, a control transfer occurs by pushing the PC onto the stack, followed by a branch to subroutines at the specified locations in the ROM. Only the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved first. External interrupts are triggered by a high to low transition of INT0 or INT1, and the related
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Register Bit No. 0 1 2 INTC0 (0BH) 3 4 5 6 7 0 1 INTC1 (1EH) 2, 3 4 5 6, 7 Label EMI EEI0 EEI1 ETI EIF0 EIF1 TF 3/4 ETBI ERTI 3/4 TBF RTF 3/4 Function Control the master (global) interrupt (1= enabled; 0= disabled) Control the external interrupt 0 (1= enabled; 0= disabled) Control the external interrupt 1 (1= enabled; 0= disabled) Control the timer/event counter interrupt (1= enabled; 0= disabled) External interrupt 0 request flag (1= active; 0= inactive) External interrupt 1 request flag (1= active; 0= inactive) Internal timer/event counter request flag (1= active; 0= inactive) Unused bit, read as 0 Control the time base interrupt (1= enabled; 0= disabled) Control the real time clock interrupt (1= enabled; 0= disabled) Unused bit, read as 0 Time base request flag (1= active; 0= inactive) Real time clock request flag (1= active; 0= inactive) Unused bit, read as 0 INTC register interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, and the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 6 of INTC0), that is caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag
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(TF) is reset, and the EMI bit is cleared to disable further interrupts. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 4 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 10H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 5 of INTC1), that is caused by a
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regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. Interrupt Source Priority Vector a b c d e External interrupt 0 External interrupt 1 Timer/event counter overflow Time base interrupt Real time clock interrupt 1 2 3 4 5 04H 08H 0CH 10H 14H status of the interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call subroutine in the interrupt subroutine may damage the original control sequence. Oscillator configuration The HT49C10 provides two oscillator circuits for system clocks, i.e., RC oscillator and crystal oscillator, determined by mask option. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Of the two oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 51kW to 1MW. The system clock,
OSC1 V
DD
OSC1
The timer/event counter interrupt request flag (TF), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable timer/event counter interrupt bit (ETI), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the interrupt control register (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), on the other hand, constitute the other interrupt control register (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ETI, ETBI, and ERTI are all used to control the enable/disable
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OSC2
fS
YS
/4
OSC2
C r y s ta l O s c illa to r
RC
O s c illa to r
System oscillator
OSC3
OSC4
RTC oscillator
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divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are needed. There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable frequency. The RTC oscillator circuit can be controlled to oscillate quickly by setting QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and turn it off after two seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78 ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by mask option. But if the WDT is disabled, all executions related to the WDT lead to no operation. After the WDT clock source is selected, it time-out period is fs/215~fs/216. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the halt instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and HALT instruction. There are two sets of software instructions, CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instructions, only one type of instruction can be active at a time depending on the mask option - CLR WDT
S y s te m
C lo c k /4 M ask O p tio n S e le c t fs D iv id e r P r e s c a le r CK T CK R T T im e - o u t R e s e t fs /2
RTC O SC 32768H z W DT OSC 12kH z
15
~ fs /2
16
W D T C le a r
Watchdog timer
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times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. Multi-function timer The HT49C10 provides a multi-function timer for WDT, time base and RTC but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fs/22 to fs/28) for LCD driver circuits, and a selectable frequency signal (ranges from fs/22 to fs/29) for buzzer output by mask option. It is recommended to select a 4kHz signal for LCD driver circuits for proper display. Time base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fs/212 to fs/215 selected by mask option. If time base time-out occurs, the related interrupt request flag (TBF; bit 4 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 10H occurs. Real time clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its
fs D iv id e r
time-out period ranges from fs/28 to fs/215 by software programming (recommand use 212~215). Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The real time clock time-out signal can also be applied as a clock source of the timer/event counter to get a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 28 29 210 211 212 213 214 215
Power down operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT
oscillator keeps running (if the WDT oscillator or the real time clock is selected). registers remain unchanged.
* The contents of the on-chip RAM and of the * The WDT is cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the real time clock oscillator).
P r e s c a le r
M a s k O p tio n
2 8
M ask O p tio n T im e B a s e In te r r u p t fs /2 1 2~ fs /2 1 5
L C D D r iv e r ( fs /2 ~ fs /2 ) B u z z e r (fs /2 ~ fs /2 )
2 9
Time base
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* All I/O ports maintain their original status. * The PD flag is set but the TO flag is cleared. * LCD driver is still running (if the WDT OSC
or RTC OSC is selected).
The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled, but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the halt status, the system cannot be awaken using that interrupt. If a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted. If the wake-up results from an interrupt
fs D iv id e r RT2 RT1 RT0
acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u means unchanged
P r e s c a le r
8 to 1 M ux.
(fs /2 ~ fs /2 ) R T C In te rru p t
8
15
Real time clock
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VDD RES S S T T im e - o u t C h ip R eset tS
ST
The functional unit chip reset status are shown below. PC Interrupt Prescaler, divider Reset timing chart
V
DD
000H Disabled Cleared Clear. After master reset, begins counting Off Input mode Points to the top of the stack
WDT, RTC, time base Timer/event counter Input/output ports SP
RES
Reset circuit
H ALT W DT W DT T im e - o u t R eset E x te rn a l C o ld R eset W a rm R eset
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
Reset configuration To guarantee that the crystal oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or awakes from the HALT state. Awaking from the HALT state or system power-up, the SST delay is added. An extra SST delay is added during the power-up period, and any wake-up from HALT may enable the SST delay only.
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The states of the registers are summarized below. Register TMR TMRC Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PB Reset (Power On) xxxx xxxx 0000 1--000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx -000 0000 --00 --00 --00 0111 1111 1111 --11 1111 WDT Time-out (Normal Operation) uuuu uuuu 0000 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu -000 0000 --00 --00 --00 0111 1111 1111 --11 1111 RES Reset (Normal Operation) uuuu uuuu 0000 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu -000 0000 --00 --00 --00 0111 1111 1111 --11 1111 RES Reset (HALT) uuuu uuuu 0000 1--000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --01 uuuu -000 0000 --00 --00 --00 0111 1111 1111 --11 1111 WDT Time-out (HALT) uuuu uuuu uuuu u--000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu --uu --uu --uu uuuu uuuu uuuu --uu uuuu
Note: * means warm reset u means unchanged x means unknown
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Timer/event counter A timer/event counter (TMR) is implemented in the HT49C10. The timer/event counter contains an 8-bit programmable count-up counter, and the clock source may come from the system clock or instruction clock (system clock/4) or RTC time-out signal or external source. System clock source or instruction clock is selected by mask option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. There are two registers related to the timer/event counter, i.e., TMR ([0DH]) and TMRC ([0EH]). And two physical registers are mapped to TMR location; writing TMR locates the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. The TMRC is a timer/event counter control register which defines some options. The TN0 and TN1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR), and the counting is based on the internal selected clock source.
S y s te m S y s te m C lo c k C lo c k /4 M ask O p tio n S e le c t M U X D a ta B u s TN2 TM R TE TN1 TN0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r T P A 3 D a ta C T R L O v e r flo w T o In te rru p t Q PFD O ut TN1 TN0 T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d R TC O ut
In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (TF; bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bits equal to one, after the TMR has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes,
Timer/event counter
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Label (TMRC) 3/4 TE TON TN2 Bits 0~2 3 4 5 Unused bits, read as 0 Defines the TMR active edge of the timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disabled; 1=enabled) Two to one multiplexer control inputs to select the timer/event counter clock source (0=RTC output; 1=system clock or system clock/4) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse Width measurement mode (external clock) 00=Unused TMRC register the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by mask option. No matter what the operation mode is, writing a 0 to ETI disables the interrupt service. When the PFD function is selected, executing CLR [PA].3 instruction to enable PFD output and executing SET [PA].3 instruction to disable the PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is t u r n e d o n , d a t a w r i t t e n t o t h e timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still goes on operating until an overflow occurs. When the timer/event counter (reading TMR) is read, the clock is blocked to avoid errors. As this may results in a counting error, this should be taken into account by the programmer. It is strongly recommended to load first a specific value into the TMR register, then turn on the timer/event counter for proper operation. Because the initial value of TMR is unknown. Input/output ports There is an 8-bit bidirectional input/output port and a 6-bit input port in the HT49C10, labeled PA and PB, which are mapped to [12H] and [14H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) and with or without pull-high resistor by mask option, PA4~PA7 always pull-high and NMOS (input/output). PB can only be used for input operation, and each bit on the port with pull-high resistor. Both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA output operation, all data are latched and remain unchanged until the output latch is rewritten. When the structures of PA are open drain NMOS type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is executing first the instruction SET [m].i (i=0~7 for PA) to disable any related NMOS device, and then MOV A, [m] to get stable data. Function
TN0, TN1
7, 6
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HT49C10
V
DD
V
DD
W EAK P u ll- u p Ma Op (o n PA Q CK S Q sk tio n ly 0~PA3) M a s k O p tio n ( o n ly P A 0 ~ P A 3 ) PA0~PA7
D a ta B u s W r ite C h ip R e s e t R e a d I/O W a k e -u p
D
S y s te m
M a s k O p tio n
PA input/output port
V
DD
W EAK P u ll- u p C h ip R e s e t R e a d I/O
PB0~PB5
PB input lines After chip reset, these input lines remain at a high level or are left floating (by mask option). Each bit of these output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H) instructions.
Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. LCD display memory The HT49C10 provides an area of embedded data memory for LCD display. This area is located from 40H to 52H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set 1, any data
43H 50H 51H 52H 0 1 B it
COM 0 1 2
40H
41H
42H
2 3 3
SEGMENT
0
1
2
3
16
17
18
Display memory
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Register Bit No. Label Read/Write Reset 0~2 RTCC (09H) 3 4 5~7 RT0 RT1 RT2 3/4 QOSC 3/4 R/W 3/4 R/W 3/4 0 3/4 0 3/4 Function 8 to 1 multiplexer control inputs to select the real time clock prescaler output Unused bits, read as 0 Control the RTC OSC to oscillate quickly. 0 enable 1 disable Unused bits, read as 0
RTCC register written into 40H~52H will affect the LCD display. When the BP is cleared 0, any data written into 40H~52H means to access the general purpose data memory. The LCD display memory can be read and written to, only by indirect addressing mode using MP1. When data is writxten into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display On or Off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the HT49C10. LCD driver output The output number of the HT49C10 LCD driver can be 192 or 193 or 184 by mask option (i.e., 1/2 duty or 1/3 duty or 1/4 duty). The bias type of LCD driver can be R type or C type. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The bias voltage of LCD driver can be 1/2 bias or 1/3 bias by mask option. If 1/2 bias is selected, a capacitor mounted between V2 pin and the ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. Please refer to the application diagram. Buzzer HT49C10 provides a pair of buzzer output BZ and BZ, which share pins with PA0 and PA1 respectively, as determined by mask option. Its output frequency can be selected by mask option. When the buzzer function is selected, setting PA.0 and PA.1 0 simultaneously will enable the buzzer output and setting PA.0 1 will disable the buzzer output.
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D u r in g a R e s e t P u ls e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l O p e r a tio n M o d e : COM0 COM1 COM2 L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g u n lit O n ly L C D s e g m e n ts o n C O M 0 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 1 s id e b e in g lit O n ly L C D s e g m e n ts o n C O M 2 s id e b e in g lit L C D s e g m e n ts o n C O M 0 ,1 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 1 ,2 s id e s b e in g lit L C D s e g m e n ts o n C O M 0 ,1 ,2 s id e s b e in g lit H a lt M o d e : C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts
VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VD 1 /2 VS
CD CD S CD CD CD CD S CD CD S CD CD S CD CD S CD S CD S D S S S S S S S S
VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D
LCD driver output (1/3 duty, 1/2 bias, R/C type)
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3 /2 V L C D VLCD 1 /2 V L C D COM0 VSS 3 /2 V L C D VLCD 1 /2 V L C D COM1 VSS 3 /2 V L C D VLCD 1 /2 V L C D COM2 VSS 3 /2 V L C D VLCD COM3 1 /2 V L C D VSS 3 /2 V L C D VLCD L C D s e g m e n ts O N C O M 2 s id e lig h te d 1 /2 V L C D VSS
LCD driver output (1/4 duty, 1/3 bias, C type)
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Mask option The following shows 16 kinds of mask options in the HT49C10. All these options should be defined in order to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 Mask Option OSC type selection. This option is to decide if an RC or crystal oscillator is selected as system clock. Clock source selection of WDT, RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by mask option. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 have been executed, the WDT can be cleared. Time Base time-out period selection. The Time Base time-out period ranges from fs/2 15 fs/2 . fs means the clock source selected by mask option.
12
to
Buzzer output frequency selection. There are eight types frequency signals for buzzer out2 9 put: fs/2 ~fs/2 . fs means the clock source selected by mask option. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. Pull-high selection. This option is to decide whether the pull-high resistance is viable or not on the PA0~PA3. PA CMOS or NMOS selection. PA0~PA3 can be selected as CMOS or NMOS structure, but PA4~PA7 are always NMOS. When the CMOS is selected, the related pins can only be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. Clock source selection of timer/event counter. There are two types of selection: system clock or system clock/4. I/O pins share with other functions selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selection: 2 commons (1/2 duty) or 3 commons (1/3 duty) or 4 commons (1/4 duty). If the 4 commons are selected, the segment output pin SEG18 will be set as a common output. LCD bias power supply selection. There are two types of selection: 1/2 bias or 1/3 bias. LCD bias type selection. This option is to decide what kind of bias is selected, R type or C type. LCD driver clock selection. There are seven types frequency signals for LCD driver circuits: 2 8 fs/2 ~fs/2 . fs means the clock source selected by mask option.
9
10 11
12 13 14 15
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HT49C10
Application Circuits
RC o s c illa to r a p p lic a tio n C r y s ta l o s c illa to r a p p lic a tio n
V
DD
OSC1 SEG 0~17 CO M 0~3 OSC2 VLCD LCD PANEL
OSC1 SEG 0~17 CO M 0~3 OSC2 LCD PANEL
fS
YS
/4 V
DD
LC D Pow er S u p p ly
V
DD
VLCD
LC D Pow er S u p p ly
C1
RES
C2
0 .1 m F
RES
C1 C2 0 .1 m F
H T49C 10
V1
H T49C 10
0 .1 m F OSC3
V1
0 .1 m F
OSC3 V2 OSC4 IN T 0 IN T 1 TM R PB0~PB5 0 .1 m F
V2 OSC4 IN T 0 IN T 1 TM R PB0~PB5 PA0~PA7
0 .1 m F
PA0~PA7
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory Z Z Z Z AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Z Z Z Z Z Z Z Z Z Z Z Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Flag Affected
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Mnemonic Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog timer Pre-clear watchdog timer Pre-clear watchdog timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode None None None TO,PD TO*,PD* TO*,PD* None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt None None None None None None None None None None None None None Clear bit of data memory Set bit of data memory None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC None** None None Description Flag Affected
Note: x: 8-bit immediate data m: 7 bits data memory address A: accumulator i: 0~7 number of bits addr: 10-bit program memory address O: Flag is affected -: Flag is not affected *: Flag may be affected by the execution status
29
**: For the old version of the E.V. chip, the zero flag (Z) can be affected by executing the MOV A,[M] instruction. For the new version of the E.V. chip, the zero flag cannot be changed by executing the MOV A,[M] instruction.
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HT49C10
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
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ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
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CALL addr Description Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4 CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to zero. [m] 00H
Clear bit of data memory The bit i of the specified data memory is cleared to zero. [m].i 0
Clear watchdog timer The WDT is cleared (re-counting from zero). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
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CLR WDT1 Description Preclear watchdog timer The TD, PD flags and WDT are all cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0* TC2 3/4 CLR WDT2 Description TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Preclear watchdog timer The TO, PD flags and WDT are cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CPL [m] Description
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. [m] [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TC2 3/4 DAA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Code Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by one. [m] [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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DECA [m] Description Operation Affected flag(s) TC2 3/4 HALT Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0 TC2 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
INC [m] Description Operation Affected flag(s)
Increment data memory Data in the specified data memory is incremented by one. [m] [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
INCA [m] Description Operation Affected flag(s)
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The contents of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
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OR A,[m] Description Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
RET Description Operation Affected flag(s)
Return from subroutine The program counter is restored from the stack. This is a two-cycle instruction. PC Stack TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). PC Stack EMI 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RL [m] Description Operation Affected flag(s)
Rotate data memory left The contents of the specified data memory are rotated one bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
RLA [m] Description
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated one bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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RLC [m] Description Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation Affected flag(s)
Rotate data memory right The contents of the specified data memory are rotated one bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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RRA [m] Description Rotate right-place result in the accumulator Data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TC2 3/4 RRC [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RRCA [m] Description
Rotate right through carry-place result in the accumulator Data of the specified data memory and the carry flag are rotated one bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
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SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag aresubtractedfromtheaccumulator,leavingtheresultintheaccumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
SDZ [m] Description
Skip if decrement data memory is zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]-1)=0, [m] ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]-1)=0, ACC ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m].i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to one. [m] FFH
Set bit of data memory Biti of the specified data memory is set to one. [m].i 1
Skip if increment data memory is zero The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]+1)=0, [m] ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if zero The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if ([m]+1)=0, ACC ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SNZ [m].i Description Skip if bit i of the data memory is not zero If bit i of the specified data memory is not zero, the next instruction is skipped. If bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m].i0 TC2 3/4 SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
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SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory-place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZ [m] Description
Skip if data memory is zero If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m]=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZA [m] Description
Move data memory to ACC, skip if zero The contents of the specified data memory are copied to the accumulator. If the contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m]=0, ACC [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SZ [m].i Description Skip if bit i of the data memory is zero If bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle). Skip if [m].i=0 TC2 3/4 TABRDC [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDL [m] Description Operation Affected flag(s)
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
XOR A,[m] Description Operation Affected flag(s)
Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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XORM A,[m] Description Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. [m] ACC XOR [m] TC2 3/4 XOR A,x Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Logical XOR immediate data to the accumulator Data in the the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The zero flag is affected. ACC ACC XOR x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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